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16.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register
Offset
0x03C
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:8
TXDATA1
0x00
W
TX Data
Second frame to write to buffer.
7:0
TXDATA0
0x00
W
TX Data
First frame to write to buffer.
16.5.17 USARTn_IF - Interrupt Flag Register
Offset
0x040
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
12
CCF
0
R
Collision Check Fail Interrupt Flag
Set when a collision check notices an error in the transmitted data.
11
SSM
0
R
Slave-Select In Master Mode Interrupt Flag
Set when the device is selected as a slave when in master mode.
10
MPAF
0
R
Multi-Processor Address Frame Interrupt Flag
Set when a multi-processor address frame is detected.
9
FERR
0
R
Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
8
PERR
0
R
Parity Error Interrupt Flag
Set when a frame with a parity error (asynchronous mode only) is received while RXBLOCK is cleared.
7
TXUF
0
R
TX Underflow Interrupt Flag
Set when operating as a synchronous slave, no data is available in the transmit buffer when the master starts transmission of a
new frame.
6
TXOF
0
R
TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
5
RXUF
0
R
RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
4
RXOF
2011-04-12 - d0001_Rev1.10
0
R
211
RX Overflow Interrupt Flag
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